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NXP LPC11xx I2C Slave 从机程序芯片解密

  1. 芯片解密/****************************************************************************
  2. *   $Id:: i2cslave.c 3635 2010-06-02 00:31:46Z usb00423                    $
  3. *   Project: NXP LPC11xx I2C Slave example
  4. *
  5. *   Description:
  6. *     This file contains I2C slave code example which include I2C slave
  7. *     initialization, I2C slave interrupt handler, and APIs for I2C slave
  8. *     access.
  9. *
  10. ****************************************************************************
  11. * Software that is described herein is for illustrative purposes only
  12. * which provides customers with programming information regarding the
  13. * products. This software is supplied "AS IS" without any warranties.
  14. * NXP Semiconductors assumes no responsibility or liability for the
  15. * use of the software, conveys no license or title under any patent,
  16. * copyright, or mask work right to the product. NXP Semiconductors
  17. * reserves the right to make changes in the software without
  18. * notification. NXP Semiconductors also make no representation or
  19. * warranty that such application will be suitable for the specified
  20. * use without further testing or modification.
  21. ****************************************************************************/
  22. #include "LPC11xx.h"/* LPC11xx Peripheral Registers */
  23. #include "type.h"
  24. #include "i2cslave.h"

  25. volatile uint32_t I2CMasterState = I2C_IDLE;
  26. volatile uint32_t I2CSlaveState = I2C_IDLE;

  27. volatile uint32_t I2CMode;

  28. volatile uint8_t I2CWrBuffer[BUFSIZE];
  29. volatile uint8_t I2CRdBuffer[BUFSIZE];
  30. volatile uint32_t I2CReadLength;
  31. volatile uint32_t I2CWriteLength;

  32. volatile uint32_t RdIndex = 0;
  33. volatile uint32_t WrIndex = 0;

  34. /*
  35. From device to device, the I2C communication protocol may vary,
  36. in the example below, the protocol uses repeated start to read data from or
  37. write to the device:
  38. For master read: the sequence is: STA,Addr(W),offset,RE-STA,Addr(r),data...STO
  39. for master write: the sequence is: STA,Addr(W),offset,RE-STA,Addr(w),data...STO
  40. Thus, in state 8, the address is always WRITE. in state 10, the address could
  41. be READ or WRITE depending on the I2C command.
  42. */   

  43. /*****************************************************************************
  44. ** Function name:I2C_IRQHandler
  45. **
  46. ** Descriptions:I2C interrupt handler, deal with master mode only.
  47. **
  48. ** parameters:None
  49. ** Returned value:None
  50. **
  51. *****************************************************************************/
  52. void I2C_IRQHandler(void)
  53. {
  54.   uint8_t StatValue;

  55.   /* this handler deals with master read and master write only */
  56.   StatValue = LPC_I2C->STAT;
  57.   switch ( StatValue )
  58.   {
  59. case 0x60:/* An own SLA_W has been received. */
  60. case 0x68:
  61. RdIndex = 0;
  62. LPC_I2C->CONSET = I2CONSET_AA;/* assert ACK after SLV_W is received */
  63. LPC_I2C->CONCLR = I2CONCLR_SIC;
  64. I2CSlaveState = I2C_WR_STARTED;
  65. break;
  66. case 0x80:/*  data receive */
  67. case 0x90:
  68. if ( I2CSlaveState == I2C_WR_STARTED )
  69. {
  70. I2CRdBuffer[RdIndex++] = LPC_I2C->DAT;
  71. LPC_I2C->CONSET = I2CONSET_AA;/* assert ACK after data is received */
  72. }
  73. else
  74. {
  75. LPC_I2C->CONCLR = I2CONCLR_AAC;/* assert NACK */
  76. }



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