EDA 汽车尾灯控制器设计VHDL源码IC解密
- IC解密Library ieee;
- IC解密Use ieee.std_logic_1164.all;
- IC解密Use ieee.std_logic_unsigned.all;
- Entity tp is
- Port(clk:in std_logic;
- Left:in std_logic;
- Right:in std_logic;
- Brake:in std_logic;
- Night:in std_logic;
- Ld1,Ld2,Ld3:out std_logic;
- Rd1,Rd2,Rd3:out std_logic);
- End;
- Architecture bh of tp is
- Component sz is
- Port(clk:in std_logic;
- Cp:out std_logic);
- End component;
- Component ctrl is
- Port(left,right,brake,night:in std_logic;
- Lp,rp,lr,brake_led,night_led:out std_logic);
- End component;
- Component lc is
- Port(clk,lp,lr,brake,night:in std_logic;
- Ledl,ledb,ledn:out std_logic);
- End component;
- Component rc is
- Port(clk,rp,lr,brake,night:in std_logic;
- Ledr,ledb,ledn:out std_logic);
- End component;
- Signal tmp0,tmp1,tmp2,tmp3,tmp4:std_logic;
- Signal err0,err1,err2,err3,err4,err5:std_logic;
- signal bm:std_logic;
- Begin
- U1:sz port map(clk,bm);
- U2:ctrl port map(left,right,brake,night,tmp0,tmp1,tmp2,tmp3,tmp4);
- U3:lc port map(clk,tmp0,tmp2,tmp3,tmp4,err0,err1,err2);
- U4:rc port map(clk,tmp1,tmp2,tmp3,tmp4,err3,err4,err5);
- Ld1<=err0 and bm;
- Ld2<=err1;
- Ld3<=err2;
- Rd1<=err3 and bm;
- Rd2<=err4;
- Rd3<=err5;
- End;
芯片解密
