芯片复制FPGA动态配置PLL输出
1、芯片复制建立.mif文件
点击file->New->memory Initialization File 设置 number of words 为144,word size 为1,保存即可,这里需要的时钟数与.mif文件数对应即可。
2、获取不同时钟对应的.mif配置文件(数据)
先配置好输出的时钟频率(Output Clocks界面进行配置)转到下图所示的界面,点击序号为2所在位置的browse ,找到刚刚保存的.mif,然后点击Generate a Cinfiguration File即可。重复上述步骤可获取不同的时钟.mif配置文件。
芯片复制源码
module vgaclk_out(
input clk,
input rst,
input[2:0] rom_swn,
output vga_clk,
output reg write_from_rom=0,
output reg reconfig=0,
output busy,
output pll_scandone
);
芯片复制wire pll_scandataout,pll_areset,pll_configupdate,pll_scanclk,pll_scanclkena,write_rom_ena,pll_scandata;
wire clk_40M,clk_108M,clk_148_5M,clk_27_175M,clk_65M,clk_74_25M;
wire [7:0]rom_address_out;
wire pll_clkout,rom_out;
pll_sw u1(
.clock(clk),
.pll_areset_in(!rst),
.pll_scandataout(pll_scandataout),
.pll_scandone(pll_scandone),
//.read_param(0),
.reconfig(reconfig),//
.reset(!rst),
//.reset_rom_address(0),
.rom_data_in(rom_out),
.write_from_rom(write_from_rom),//
//.write_param(0),
//.counter_param(0),
.pll_scandata(pll_scandata),
//.counter_type(0),
//.data_in(0),
//.data_out(),
.pll_areset(pll_areset),
.pll_configupdate(pll_configupdate),
.pll_scanclk(pll_scanclk),
.pll_scanclkena(pll_scanclkena),
.write_rom_ena(write_rom_ena),
.rom_address_out(rom_address_out),
.busy(busy)
);
wire clk_out;
vga_pll u2(
.areset(pll_areset),
.configupdate(pll_configupdate),
.scanclk(pll_scanclk),
.scanclkena(pll_scanclkena),
.scandata(pll_scandata),
.scandataout(pll_scandataout),
.scandone(pll_scandone),
.inclk0(clk),
.c0(vga_clk)
);

芯片解密