verilog数字时钟程序 单片机解密
单片机解密程序部分
module shizhong(input CLK,
output reg[5:0] miao,fen,shi);
reg JW,jw;
always @(posedge CLK )
begin
case(miao)
6'B111011:begin miao=0;JW=1;end
default:begin miao=miao+1;JW=0;end
endcase
end
always @(posedge JW )
begin
case(fen)
6'B111011:begin fen=0;jw=1;end
default:begin fen=fen+1;jw=0;end
endcase
end
always @(posedge jw )
begin
case(shi)
6'B000001:begin shi=0;end
default:begin shi=shi+1;end
endcase
end

芯片解密